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Showing posts from April, 2012

Estonian

Image
Our Electrical Engineering Department at Auburn University has a list service that they use to send out email notifications. Usually it's general stuff such as recruitment events, new classes opening up, etc. The other day, when I opened up an email from them, Google Chrome thought the email was in Estonian! See screenshot below... :-)


Computer Systems Class Notes 2012/04/16

Mon Apr 16 11:08:14 CDT 2012
Serial: • Serial transfer
– Single-bit Data Width
– Simpler Interface, less hardware • Transfer modes
– Simplex (only send or receive)
– Half duplex
– Full duplex • Asynchronous serial transfer (SCI)
– No common clock
– Each character is framed by a preceding ‘start’ bit, LSBÆMSB, and one or more
‘stop’ bits.
– “1 to 0” transition (following the stop (& mark) bits of 1) signals the beginning of a
character.
– High overhead since each character is framed individually. • Synchronous serial transfer
– Common clock
S
– Low overhead [SYN] [SYN] [STX] [pure data bytes] [ETX] • Interface -------------
----> | interface | ----->
-------------
Parallel data bus Serial data line – Conversion between ‘serial’ and ‘parallel’
– Framing
– Handshaking
• HCS12 Serial I/O
- Both asynchronous and synchronous serial I/O interfaces • Asynchronous Serial Communication Interface (SCI)
– UART UART (Universal Asynchronous Receiver-TT itt ) ransmitter) • Sy…

Computer Systems Class Notes 2012/04/11

Wed Apr 11 11:02:35 CDT 2012Memory:
A15 A11 A7 A3 A0
chip 0 address range: $0000 - $0FFF (0000 0000 0000 0000 ->
0000 1111 1111 1111)
chip 1 address range: $1000 - $2FFF (0001 0000 0000 0000 ->
0001 1111 1111 1111)
chip 3 address range: $2000 - $3FFF (0011 0000 0000 0000 ->
0011 1111 1111 1111) A15-A12 Decoder Enable
A11-A08 Chip Select
A07-A00 Address within a chip |==========| |==================|
A13------------|1A 1Y0|o----------|A11-0 D7-0 |
A12------------|1B 1Y1|o-----| | |
| 1Y2| | |CS(bar) R/W(bar)|
==== | 1Y3| | ==================
A15--| OR |----|1E | |
A14--| | | | |
==== | | |
==========
Alas, drawing in ASCII isn't very efficient...moving on... 16-bit uprocessor (16 address bits A15-0)
The data bus is 8-bits wide. (…

Computer Systems Class Notes 2012/04/09

Mon Apr 9 11:02:24 CDT 2012
# Memory Systems:
Memory System Hierarcy
-Disk, ROM, RAM, Cache
# Memory module (chip) org.
- On-chip (address) decoder, cell array
Address Decoding
# Memory Remapping
# Memory Expansion RAM (Random Access Memory) ROM (Read-Only Memory) Types of ROM:
* Mask-programmed ROM (MROM)
-factory set.
* PROM (Programmable ROM)
-fuses --irreversable
* EPROM (Erasable PROM)
-erases with UV light
* Flash EPROM
-usec-faster --erase block by block
* EEPROM (Electrically Erasable PROM) RAM: Static and Dynamic
* Static
-Each cell is a flip-flop storing 1 bit of info. * Dynamic RAM
-Each cell is a capacitor...needs to be refreshed periodically to retain the 1-bit info.
-Cheap
-A refresh is accomplished if you read and then write back.
Refresh overhead 4 Mbyte DRAM: refreshed 4 msec
(2048 * 80e-9) / 4e-3 = blah RAM Structure:
- Select
- Data In
- Data Out
- R/W
- 1-byte contains 8 memory cells.
- Common data lines such as Select and R/W.
- Wit…