Computer Systems Class Notes 2012/04/09


Mon Apr 9 11:02:24 CDT 2012
# Memory Systems:
Memory System Hierarcy
-Disk, ROM, RAM, Cache
# Memory module (chip) org.
- On-chip (address) decoder, cell array
Address Decoding
# Memory Remapping
# Memory Expansion

RAM (Random Access Memory)

ROM (Read-Only Memory)

Types of ROM:
* Mask-programmed ROM (MROM)
-factory set.
* PROM (Programmable ROM)
-fuses --irreversable
* EPROM (Erasable PROM)
-erases with UV light
* Flash EPROM
-usec-faster --erase block by block
* EEPROM (Electrically Erasable PROM)

RAM: Static and Dynamic
* Static
-Each cell is a flip-flop storing 1 bit of info.

* Dynamic RAM
-Each cell is a capacitor...needs to be refreshed periodically to retain the 1-bit info.
-Cheap
-A refresh is accomplished if you read and then write back.
Refresh overhead

4 Mbyte DRAM: refreshed 4 msec
(2048 * 80e-9) / 4e-3 = blah

RAM Structure:
- Select
- Data In
- Data Out
- R/W
- 1-byte contains 8 memory cells.
- Common data lines such as Select and R/W.
- With an n-bit address, you can have 2^n bytes of storage.

{picture of 2 x 4 decoder for 4 x 8 memory array }

Decoders:
'138 CBA (C is MSB)
'139 AB (A is MSB)

Expand Memory Word Size:
m -> m x 2^k

Expand Number of Memory Words
2^n -> 2^n x 2^l
2^l => memory chips

Memory Chip: 4 x 8
5-bit uproc (A_4 ... A_0)
A memory system of 16 bits...

Example: A memory chip is 4 x 8
2^n x m = 4 x 8 m = 8, n = 2
on-chip decoder -> n x 2^n => 2 x 4
# of address pins to each memory chip is n=2.
We have a 5-bit uprocessor. (A_4 ... A_0)
Design a memory system of 16-bytes (a very tiny memory system)

We need to expand the # of memory words:
# of memory chips = 16-bytes / 4 bytes per chip = 4 chips = 2^l, l = 2
l + n = address bits.
2 + 2 = 4
So we need 4 address bits total!

  • Lower 2 address bits are connected to all of the memory chips (?) (A_1,A_0)
  • The upper l (2) adress bits are inputs to the external decoder... l x 2^l => 2 x 4 (A_3,A_2)
  • Remaining address bit (A_4) are connected to our external decoder enable.


A memory system of 16-kbytes for addresses $0000 -> $3FFF (4000 hex values)

Each memory chip is arranged 2^12 x 8 (2^12 = 4096) n=12, m=8
Our on-chip address decoder for each chip -> n x 2^n = 12 x 2^12 = 12 x 4096
# of address lines to each memory chip is n=12 (A_11 ... A_0)
m=8 data bits (D_7 ... D_0)

16-bit uprocessor: (Adress pins A_15 ... A_0)
Need a memory system of 16kB with addresses $0000 -> $3FFF
# of memory chips needed = total memory (16kB) / kB per chip (4kB) = 4 chips total = 2^l chips
n+l address bits => 12+2 = 14 address bits

  • Lower n (12) bits are connected to all of the memory chips (A_11 ... A_0)
  • Upper l(2) are inputs to our external decoder of size l x 2^l -> 2 x 4 (A_13 ... A_12)
  • Decoder enable = remaining address bits (A_15,A_14)
  • We have a R/W signal that is connected to all memory chips.
  • Each memory chip as an active-low chip select/enable.


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