Computer Systems Class Notes 2012/04/16


Mon Apr 16 11:08:14 CDT 2012
Serial:

• Serial transfer
– Single-bit Data Width
– Simpler Interface, less hardware

• Transfer modes
– Simplex (only send or receive)
– Half duplex
– Full duplex

• Asynchronous serial transfer (SCI)
– No common clock
– Each character is framed by a preceding ‘start’ bit, LSBÆMSB, and one or more
‘stop’ bits.
– “1 to 0” transition (following the stop (& mark) bits of 1) signals the beginning of a
character.
– High overhead since each character is framed individually.

• Synchronous serial transfer
– Common clock
S
– Low overhead

[SYN] [SYN] [STX] [pure data bytes] [ETX]

• Interface

-------------
----> | interface | ----->
-------------


Parallel data bus Serial data line

– Conversion between ‘serial’ and ‘parallel’
– Framing
– Handshaking


• HCS12 Serial I/O
- Both asynchronous and synchronous serial I/O interfaces

• Asynchronous Serial Communication Interface (SCI)
– UART UART (Universal Asynchronous Receiver-TT itt ) ransmitter)

• Synchronous Serial Peripheral Interface (SPI)
– High-speed

...

Parity:
Even: 1 if # of 1's in the data byte is odd.
0 if # of 1's in the data byte is even.

Odd: 1 if # of 1's in the data byte is even.
0 if # of 1's in the data byte is odd.

====================================================
| Data | Even Parity Bit | Odd Parity Bit |
====================================================
| 0000 0000 | 0 | 1 |
| 1010 1000 | 1 | 0 |
| 1111 1111 | 0 | 1 |
| | | |
====================================================

Baud Rate Control Register:
....

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